1. Field of the Invention
The present invention relates to a semiconductor device in which a second wiring metal layer is formed on a first metal wiring layer through an insulating interlayer and wire bonding is performed for the second metal wiring layer and, more particularly, to prevention of cracking of the insulating interlayer formed immediately below a bonding region.
2. Description of the Related Art
In a conventional bipolar transistor, an emitter region is formed in a comb-like shape in order to reduce an output capacitance, improve high-frequency characteristics, and satisfy a need for increasing an output capacity. The emitter region is formed in a surface part of a base region. The base region is formed in a major surface region of a semiconductor substrate which serves as a collector region. A comb-like emitter electrode is formed on the emitter region so as to correspond to the emitter region. A comb-like base electrode is formed on the base region. The emitter and base electrodes are formed such that teeth of the electrodes are arranged in an interdigital manner at predetermined intervals.
In order to effectively utilize an active region of a transistor, a multilayered structure is utilized in which bonding pads are formed on the emitter and base electrodes through an insulating interlayer. In this case, base and emitter bonding pads are used. The base bonding pad is connected to part of the base electrode through a contact hole formed in the insulating interlayer. The emitter bonding pad is connected to part of the emitter electrode through another contact hole formed in the insulating interlayer. Base and emitter deriving bonding wires are respectively bonded to the bonding pads by thermocompression bonding.
With the above arrangement, the active region can be effectively utilized, and resistances from the emitter and base regions to the corresponding bonding wires can be reduced. In addition, the dynamic characteristics of the transistor can also be improved.
With the above arrangement, however, mechanical stress acts on the insulating interlayer by a pressure during bonding of base and emitter deriving bonding wires. The insulating interlayer is formed on the interdigital base and emitter electrodes, i.e., a portion having a large three-dimensional pattern. Therefore, a three-dimensional portion is formed on the surface of the insulating interlayer accordingly. A bonding pressure tends to be concentrated on a step of the three-dimensional pattern on the surface of the insulating interlayer. For this reason, a crack tends to occur in the insulating interlayer. In the worst case, the insulating interlayer is destroyed. Such a crack cannot be easily found by an initial electrical function test. Therefore, reliability of the semiconductor device is undesirably degraded.